module siggen_top (
    input  sys_clk,
    input  arst_n,
    input  uart_rx,
    output uart_tx,
    output sig_o
);

  wire uart_tx_busy_s;
  wire uart_rdy_s;
  wire uart_rdy_clr_s;
  wire [7:0] uart_rx_data_s;

  wire [31:0] div_factor_s;

  wire rstn_sync;

  sys_rgu rgu_inst (
      .sys_clk(sys_clk),
      .arst_n(arst_n),
      .rstn_sync(rstn_sync)
  );

  uart #(
      .CLK_FREQ  (3000000),
      .BAUDRATE  (115200),
      .OVERSAMPLE(2)
  ) uart_intf (
      .sys_clk(sys_clk),
      .rst_n(rstn_sync),
      .din(uart_rx_data_s),
      .wr_en(uart_rdy_s & (~uart_tx_busy_s)),
      .tx(uart_tx),
      .tx_busy(uart_tx_busy_s),
      .rx(uart_rx),
      .rdy(uart_rdy_s),
      .rdy_clr(uart_rdy_clr_s),
      .dout(uart_rx_data_s)
  );

  factor_update #(
      .HEAD_BYTE(8'haa)
  ) factor_update_inst (
      .sys_clk(sys_clk),
      .rst_n(rstn_sync),
      .uart_rdy_i(uart_rdy_s),
      .uart_rx_data_i(uart_rx_data_s),
      .uart_rdy_clr_o(uart_rdy_clr_s),
      .div_factor_o(div_factor_s)
  );

  sig_gen #(
      .CNT_WIDTH(32)
  ) sig_gen_inst (
      .sys_clk(sys_clk),
      .rst_n(rstn_sync),
      .div_factor(div_factor_s),
      .sig_o(sig_o)
  );

endmodule
